View ML7029_1280474.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

OKI Semiconductor ML7029
Multifunction ADPCM CODEC
FEDL7029-03
Issue Date: Feb. 18, 2004
GENERAL DESCRIPTION
The ML7029 is a single channel ADPCM CODEC IC which performs mutual transcoding between the analog voice band signal and 32 kbps ADPCM serial data.
FEATURES
* Single 3 V Power Supply Operation (VDD: 2.7 to 3.6 V) * ADPCM Algorithm: ITU-T G.726 (32 kbps, 24 kbps, 16 kbps) * Full-Duplex Transmit/Receive Operation * Transmit/Receive Synchronous Mode Only * PCM Data Format: -law * Serial PCM/ADPCM Transmission Data Rate: 64 kbps to 2048 kbps (when SYNC = 8 kHz) * Low Power Consumption Operating Mode: 18 mW Typ. (VDD = 3.0 V, SYNC = 8 kHz) Power-Down Mode: 0.03 mW Typ. (VDD = 3.0 V, SYNC = 8 kHz) * Sampling Frequency: 6 kHz to 21 kHz selectable (However, there are limitations to 16 kHz or higher frequencies) * Master Clock Frequency: Sampling frequency x 1296 When SYNC = 8 kHz: 10.368 MHz * Transmit/Receive Mute, Transmit/Receive Programmable Gain Control * Side Tone Path with Programmable Attenuation (8-Step Level Adjustment) * Serial MCU Interface Control * Package: 30-pin plastic SSOP (SSOP30-P-56-0.65-K) (ML7029)
1/29
FEDL7029-03
OKI Semiconductor
ML7029
BLOCK DIAGRAM
CR2-B7 AIN- 20 k GSX A/D Conv.
TXON/ OFF
CR2-B6 to B4 BPF/ LPF
PCM Compander
PCMSO PCMSI
ADPCM CR3-B7 to B5 CR2-B3 VFRO 20 k D/A Conv. LPF CR2-B2 to B0 VREF
RXON/ OFF
IS IR PCMRO
PCM Expander
PCMRI
SG
BCLK MCU I/F SYNC
DIN
DEN
DOUT
EXCK
MCK
PDN
VD
VA
DG
AG
2/29
FEDL7029-03
OKI Semiconductor
ML7029
PIN CONFIGURATION (TOP VIEW)
GSX NC AIN- NC SG NC VA NC AG NC VFRO NC NC DG PDN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VD BCLK SYNC PCMSO PCMSI IS IR PCMRO PCMRI NC MCK DEN EXCK DIN DOUT
NC: No Connection 30-Pin Plastic SSOP
3/29
FEDL7029-03
OKI Semiconductor
ML7029
PIN FUNCTIONAL DESCRIPTIONS
AIN-, GEX Transmit analog input and transmit level adjustment. AIN- is connected to the inverting input of the transmit amplifier. GSX is connected to the transmit amplifier output. During power-down mode, the GSX output is a high impedance state.
VFRO Receive analog output. During power-down mode, the VFRO output is in a high impedance state.
SG Analog signal ground. The output voltage of this pin is approximately 1.4 V. Put 10 F plus 0.1 F (ceramic type) bypass capacitors between this pin and AG. During power-down, this output voltage is 0 V. This pin should be used via a buffer if used externally.
AG Analog ground.
DG Digital ground. This ground is separated from the analog signal ground pin (AG). The DG pin must be kept as close as possible to AG on the PCB.
Va Analog +3 V power supply.
VD Digital +3 V power supply. This power supply is separated from the analog signal power supply pin (VA). The VD pin must be kept as close as possible to VA on the PCB. PDN Power-down and reset control input. A "0" level makes the IC enter a power-down state. At the same time, all control register data are reset to the initial state. Set this pin to "1" during normal operating mode. The power-down state is controlled by a logical OR with CR0-B5 of the control register. When using PDN for power-down and reset control, set CR0-B5 to digital "0". The reset width (a "L" level period) should be 200 ns or more. Be sure to reset the control registers by executing this power down to keep this pin to digital "0"level for 200 ns or longer after the power is turned on and VDD exceeds 2.7 V.
4/29
FEDL7029-03
OKI Semiconductor
ML7029
MCK Master clock input. The frequency is 1296 times the SYNC signal. For example, it is 10.368 MHz when the SYNC signal is 8 kHz. The master clock signal may be asynchronous with BCLK and SYNC.
PCMSO Transmit PCM data output. PCM is output from MSB in synchronization with the rising edge of BCLK and XSYNC. Refer to Figure 1. During power-down, the PCMSO output is at "L" level.
PCMSI Transmit PCM data input. This signal is converted to the transmit ADPCM data, PCM is shifted in synchronization with the falling edge of BCLK. Normally, this pin is connected to PCMSO. Refer to Figure 1.
PCMRO Receive PCM data output. PCM is the output signal after ADPCM decoder processing. This signal is output serially from MSB in synchronization with the rising edge of BCLK and RSYNC. Refer to Figure 1. During power-down, the PCMRO output is at "L" level.
PCMRI Receive PCM data input. PCM is shifted on the rising edge of the BCLK and input from MSB. Normally, this pin is connected to PCMRO. Refer to Figure 1.
IS Transmit ADPCM signal output. After having encoded PCM with ADPCM, the signal is output from MSB in synchronization with the rising edge of BCLK and XSYNC. Refer to Figure 1. This pin is at "H" level during power-down.
IR Receive ADPCM signal input. This input signal is shifted serially on the falling edge of BCLK and SYNC and input from MSB. Refer to Figure 1.
BCLK Shift clock input for the PCM and ADPCM data. The frequency is set in the range of 8 to 256 times the SYNC frequency. Refer to Figure 1.
5/29
FEDL7029-03
OKI Semiconductor
ML7029
SYMC Sampling input for the PCM and ADPCM data. The frequency is 8 kHz or 11.025 kHz and is selected by the control register data CR3-B1. Synchronize this signal with BCLK signal. SYNC is used to indicate the MSB of the PCM data stream. Refer to Figure 1.
125 s (SYNC = 8 kHz) SYNC BCLK PCMSO/PCMSI/ PCMRO/PCMRI IS/IR MSB MSB LSB LSB
Figure 1 PCM and ADPCM Interface Basic Timing
6/29
FEDL7029-03
OKI Semiconductor
ML7029
DEN, EXCK, DIN, DOUT Serial control ports for MCU interface. Reading and writing data are performed by an external MCU through these pins. The 8-byte cotrol registers (CR0 to 7) are provided on the device. DEN is the "Enable" control signal input, EXCK is the data shift clock input, DIN is the address and data input, and DOUT is the data output. Figures 2-1 and 2-2 show the input/output timing diagram. During power-down, the DOUT output is in a high impedance state.
DEN EXCK DIN DOUT W A2 A1 B7 B6 B5 A0 High Impedance B4 B3 B2 B1 B0
(a) Data Write Timing Diagram DEN EXCK DIN DOUT R A2 High Impedance A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
(b) Data Read Timing Diagram
Figure 2-1 MCU Interface Input/Output Timing (DIN = 12 bits)
DEN EXCK DIN DOUT (a) Data Write Timing Diagram W A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
High Impedance
DEN EXCK DIN DOUT R A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
High Impedance
(b) Data Read Timing Diagram
Figure 2-2 MCU Interface Input/Output Timing (DIN = 16 bits)
7/29
FEDL7029-03
OKI Semiconductor
ML7029
Table 1 shows the register map.
Table 1 Control Register Map
Name CR0 CR1 CR2 CR3 Address A2 A1 A0 0 0 0 0 0 0 1 1 0 1 0 1 Control and Detect Data B5 B4 B3 B2 PDN ALL TX RESET TX GAIN1 GAIN0 -- RX RESET TX GAIN0 -- -- TX MUTE RX ON/OFF -- -- RX MUTE RX GAIN2 -- R/W R/W R/W R/W R/W
B7 --
B6 --
B1 -- -- RX GAIN1 HPF 8k/11k
B0 -- RX PAD RX GAIN0 HPF ON/OFF
MODE 1 MODE 0 TX ON/OFF TX GAIN2 GAIN1
Side Tone Side Tone Side Tone
GAIN2 R/W : Read/Write enable
8/29
FEDL7029-03
OKI Semiconductor
ML7029
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN Tstg Condition -- -- -- -- Rating -.3 to +5.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -55 to +150 Unit V V V C
RECOMMENDED OPERATION CONDITIONS
Parameter Power Supply Voltage Operating Temperature Range Digital Input High Voltage Digital Input Low Voltage Master Clock Frequency Master Clock Frequency Accuracy Bit Clock Duty Sampling Frequency (*1) Master Clock Duty Ratio Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time PCM Sync Signal Setting Time (Continuous BCLK) PCM Sync Signal Setting Time (Burst Mode Clock) SYNC Signal Width (Continuous BCLK) SYNC Signal Width (Burst Mode Clock) PCM, ADPCM Setup Time PCM, ADPCM Hold Time Digital Output Load Bypass Capacitors for SG *1: Refer to the Appendix. Symbol VDD Ta VIH VIL fMCK1 fMCK2 fBCK fSYNC DMCK DCLK tir tif tBS tSB tWS tWSB tDS tDH CDL CSG Condition Voltage must be fixed -- Digital Input Pins Digital Input Pins MCK MCK BCLK SYNC MCK (20.736 MHz) BCLK, EXCK Digital Input Pins Digital Input Pins BCLK SYNC (see Fig. 3-1) BCLK SYNC (see Fig. 3-2) SYNC (see Fig. 3-1) SYNC (see Fig. 3-2) -- -- Digital Output Pins SG to AG Min. +2.7 -25 0.45 x VDD 0 7.776 -0.01% SYNC x 8 6.0 30 30 -- -- 100 0 1BCLK 1BCLK 100 100 -- 10+0.1 Typ. 3.0 +25 -- -- 10.368 SYNC x 1296 -- 8.0 50 50 -- -- -- -- -- -- -- -- -- -- Max. +3.6 +70 VDD 0.16 x VDD 20.736 +0.01% SYNC x 256 16 70 70 50 50 -- 20 SYNC -1 BCLK Burst Clock -1 -- -- 100 -- Unit V C V V MHz MHz kHz kHz % % ns ns ns s s s ns ns pF F
9/29
FEDL7029-03
OKI Semiconductor
ML7029
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 to 3.6 V, Ta = -25 to +70C) Parameter Power Supply Current (VDD = 3.0 V, SYNC = 8 kHz) Input Leakage Current Output High Voltage Output Low Voltage Input Capacitance Symbol IDD1 IDD2 IIH IIL VOH VOL CIN Condition Operating Mode No Signal Power Down Mode (Input pins are fixed) VI = VDD VI = 0 V IOH = 4 mA IOL = -4 mA -- Min. -- -- -- -- 2.4 -- -- Typ. 6.0 0.01 -- -- -- -- 5 Max. 12 0.1 2.0 0.5 -- 0.4 -- Unit mA mA A A V V pF
Analog Interface Characteristics
(VDD= 2.7 to 3.6 V, Ta = -25 to +70C) Parameter Input Resistance Output Load Resistance Output Load Capacitance Output Amplitude (*2) Offset Voltage SG Output Voltage SG Output Resistance SG Warm-up Time Symbol RIN RL CL VO1 VOF VSG RSG TSG Condition AIN- GSX, VFRO GSX, VFRO GSX, VFRO (RL = 20 k) GSX, VFRO SG SG SGAG 10+0.1F (Rise time to max. 90% level) Min. -- 20 -- -- -100 -- -- -- Typ. 10 -- -- -- -- 1.4 40 700 Max. -- -- 100 1.3 +100 -- -- -- Unit M k pF VPP mV V k ms
*2: -7.7 dBm (600) = 0 dBm0, +3.17 dBm0 = 1.3 VPP
10/29
FEDL7029-03
OKI Semiconductor
ML7029
AC Characteristics
(VDD = 2.7 to 3.6 V, Ta = -25 to +70C) Parameter Transmit Frequency Response SYNC = 8 kHz BPF Symbol
LB8T1 LB8T2 LB8T3 LB8T4 LB8T5 LB11T1
Transmit Frequency Response SYNC = 11.025 kHz BPF Transmit Frequency Response SYNC = 8 kHz LPF Transmit Frequency Response SYNC = 11.025 kHz LPF Receive Frequency Response SYNC = 8 kHz LPF Receive Frequency Response SYNC = 11.025 kHz LPF Transmit S/N Ratio SYNC = 8 kHz (*3) Receive S/N Ratio SYNC = 8 kHz (*3) Transmit S/N Ratio SYNC = 16 kHz (*3) Receive S/N Ratio SYNC = 16 kHz (*3) Idle Channel Noise SYNC = 8 kHz (*3) Idle Channel Noise SYNC = 16 kHz (*3) Absolute Signal Amplitude (*5)
LB11T2 LB11T3 LB11T4 LB11T5 LL8T1 LL8T2 LL8T3 LL8T4 LL11T1 LL11T2 LL11T3 LL11T4 LL8R1 LL8R2 LL8R3 LL8R4 LL11R1 LL11R2 LL11R3 LL11R4 SD8T1 SD8T2 SD8R1 SD8R2 SD16T1 SD16T2 SD16R1 SD16R2
Condition Freg. (Hz) 60 300 1015 3400 3970 60 300 1400 4690 5470 300 1015 3400 3970 300 1400 4690 5470 300 1015 3400 3970 300 1400 4690 5470 f = 1015 Hz f = 1015 Hz f = 1015 Hz f = 1015 Hz -- -- 1015 Hz(GSX) SYNC = 8 kHz 1015 Hz(VFRO) SYNC = 8 kHz
Level (dBm0)
Min. 30 -0.5
Typ.
Max. -- 1.5 1.0 -- -- 1.5 1.0 -- 0.5 1.0 -- 0.5 1.0 -- 0.5 1.0 -- 0.5 1.0 -- -- -- -- -- -- -- -- -- -68 -72 -68 -72 0.359 0.359
Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
dBm0pP dBm0pP dBm0pP dBm0pP
0
0
0
0
0
0
3 -40 3 -40 3 -40 3 -40
AIN- = SG
NIDLT NIDLR NIDLT NIDLR AVT AVR
(*4)
AIN- = SG
(*4) 0 0
-- -- Reference -0.5 -- 12 -- 30 -- -0.5 -- Reference -0.5 -- 12 -- -0.5 -- Reference -0.5 -- 12 -- -0.5 -- Reference -0.5 -- 12 -- -0.5 -- Reference -0.5 -- 12 -- -0.5 -- Reference -0.5 -- 12 -- 35 -- 28 -- 35 -- 28 -- 35 -- 28 -- 35 -- 28 -- -- -- -- -- -- -- -- -- 0.285 0.320 0.285 0.320
Vrms Vrms
*3: Use the P-message weighted filter *4: PCMRI input code "11111111" (-law) *5: 0.320 Vrms = 0 dBm0 = -7.7 dBm (600)
11/29
FEDL7029-03
OKI Semiconductor
ML7029
Digital Interface
Parameter Digital Input/Output Setting Time Symbol
tSDX, tSDR tXD1, tRD1 tXD2, tRD2 tXD3, tRD3
Condition
(VDD = 2.7 to 3.6 V, Ta = -20 to +70C) Reference Min. Typ. Max. Unit 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 200 200 200 200 -- -- -- -- -- -- -- 50 -- -- 50 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz Fig. 3-1 Fig. 3-2 0 0 0 50 50 50 50 100 50 50 0 50 50 0
1LSTTL+100 pF
t1 t2 t3 t4 Serial Port Digital Input/Output Setting Time t5 t6 t7 t8 t9 t10 t11 Shift Clock Frequency fEXCK EXCK EXCK CL= 50 pF Fig. 4-1 Fig. 4-2
--
AC Characteristics (Programmable Gain Stages)
(VDD = 2.7 to 3.6 V, Ta = -25 to +70C) Parameter Gain Accuracy Symbol DG Condition All stages, to programmed value SYNC = 8 kHz Min. -1 Typ. 0 Max. +1 Unit dB
12/29
FEDL7029-03
OKI Semiconductor
ML7029
TIMING DIAGRAM
Transmit Side PCM/ADPCM Data Interface
tBS tBS SYNC tXD1 MSB tSDX tXD3 IS tSDX MSB LSB tWS tXD2
BCLK
tXD3 LSB
PCMSO
Receive Side PCM/ADPCM Data Interface
BCLK
tBS tBS tWS tRD2 tRD3 LSB tDH tRD3 LSB
SYNC tRD1 PCMRO tSDR IR MSB
tDS MSB
Figure 3-1 PCM/ADPCM Data Interface (Continuous BCLK)
13/29
FEDL7029-03
OKI Semiconductor
ML7029
Transmit Side PCM/ADPCM Data Interface
BCLK
tSB
tWSB tXD1 MSB tXD3 tXD2
SYNC
tXD3 LSB
PCMSO
IS
MSB
LSB
Receive Side PCM/ADPCM Data Interface
BCLK
tSB tWSB
SYNC
tRD1 MSB
tRD2
tRD3 LSB tDH tRD3 LSB
PCMRO
tDS IR MSB
Figure 3-2 PCM/ADPCM Data Interface (Burst Mode Clock)
14/29
FEDL7029-03
OKI Semiconductor
ML7029
Serial Port Data Transfer for MCU Interface
DEN t2 EXCK t1 1 t3 t4 2 3 t6 A2 A1 4 t7 A0 B7 t8 B7 B6 B6 B1 B1 t5 5 6 11 12 t9 t 10
DIN DOUT
W/R
B0 t 11 B0
Figure 4-1 Serial Control Port Interface (DIN = 12 bits)
DEN t2 EXCK t1 t3 t4 t6 t7 1 2 3 4 t5 5 6 12 13 14 15 16
t9
DIN
W/R
A2
A1
A0
B7 t8
B6
B0
0
DOUT
B7
B6
B0
0
Figure 4-2 Serial Control Port Interface (DIN = 16 bits)
15/29
FEDL7029-03
OKI Semiconductor
ML7029
FUNCTIONAL DESCRIPTION
Control Registers (1) CR0 (Basic operating mode setting)
B7 CR0 Initial Value -- * B6 -- * B5 PDN ALL 0 B4 -- * B3 -- * B2 -- * B1 -- * B0 -- *
Note: Initial Value: Reset state by PDN (*: Don't care) B7, B6, B4 to B0: Not used (These pins are used to test the device. They should be set to "0" during normal operation.) B5: Power-down (entire system); 0/Power-on, 1/Power-down 0 Red with the inverted external power-down signals. When using this data, set the RDN pin to "1".
(2) CR1 (ADPCM operating mode setting)
B7 CR1 Initial Value MODE1 0 B6 MODE0 0 B5 0 B4 0 B3 0 B2 0 B1 -- * B0 RX PAD 0
TX RESET RX RESET TX MUTE RX MUTE
B7, B6:
ADPCM data compression algorithm select (output bit select); (0, 0): 4-bit output (32 kbps) (0, 1): 8-bit output (64 kbps) (1, 0): 3-bit output (24 kbps) (1, 1): 2-bit output (16 kbps) Data rates in parentheses: when SYNC = 8 kHz
B5: B4: B3: B2: B1: B0:
ADPCM of transmit reset (specified by G.726); 1/Reset* ADPCM of receive reset (specified by G.726); 1/ Reset* ADPCM transmit data mute; 1/Mute ADPCM receive data mute; 1/Mute Not used (This pin is used to test the device. It should be set to "0" during normal operation. Receive side PAD; 1/inserted in the receive side voice path, 12 dB loss 0/no PAD
* The reset width should be 1/f sample s or more. The transmit and receive sides cannnot be reset separately. They must be reset at the same time.
16/29
FEDL7029-03
OKI Semiconductor
ML7029
(3) CR2 (PCM CODEC operating mode setting and transmit/receive gain adjustment)
B7 CR2 Initial Value B6 B5 B4 B3 RX ON/OFF 0 B2 B1 B0
TX ON/OFF TX GAIN2 TX GAIN1 TX GAIN0 0 0 1 1
RX GAIN2 RX GAIN1 RX GAIN0 0 1 1
B7:
Transmit PCM signal ON/OFF;
0/ON, 1/OFF
B6, B5, B4: Transmit signal gain adjustment, refer to Table 2. B3: Receive PCM signal ON/OFF; 0/ON, 1/OFF
B2, B1, B0: Receive signal gain adjustment, refer to Table 2.
Table 2 Transmit/Receive Gain Setting (when SYNC = 8 kHz)
B6 0 0 0 0 1 1 1 1 B5 0 0 1 1 0 0 1 1 B4 0 1 0 1 0 1 0 1 Transmit Gain -6 dB -4 dB -2 dB 0 dB +2 dB +4 dB +6 dB +8 dB B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Receive Gain -6 dB -4 dB -2 dB 0 dB +2 dB +4 dB +6 dB +8 dB
17/29
FEDL7029-03
OKI Semiconductor
ML7029
(4) CR3 (Side tone gain setting)
B7 CR3 Initial Value B6 B5 B4 -- * B3 -- * B2 -- * B1 HPF 8k/11k 0 B0 HPF ON/OFF 0
Side Tone Side Tone Side Tone GAIN2 GAIN1 GAIN0 0 0 0
B7, B6, B5: Side tone path gain setting. Refer to Table 3. B4 to B2: Not used (These pins are used to test the device. They should be set to "0" during normal operation.) Table 3 Side Tone Pash Gain Setting (when SYNC = 8 kHz)
B7 0 0 0 0 1 1 1 1 B6 0 0 1 1 0 0 1 1 B5 0 1 0 1 0 1 0 1 Side Tone Path Gain OFF -21 dB -19 dB -17 dB -15 dB -13 dB -11 dB -9 dB
B1:
B0:
Transmit HPF cut-off frequency select; 0/The cut-off frequency of the transmit HPF is the sampling frequency x 0.0275. When SYNC = 8 kHz: 220 Hz, when SYNC = 11.025 kHz: 300 Hz. The transmit frequency characteristics are not guaranteed when selecting SYNC = 11.025 kHz. 1/The cut-off frequency of the transmit HPF is the sampling frequency x 0.0200. When SYNC = 8 kHz: 160 Hz, when SYNC = 11.025 kHz: 220 Hz. The transmit frequency characteristics are not guaranteed when selecting SYNC = 8 kHz. Transmit HPF ON/OFF; 0/ON, 1/OFF
For the frequency characteristics, refer to Figures 9 to 12 in the Reference Data.
18/29
FEDL7029-03
OKI Semiconductor
ML7029
APPLICATION CIRCUIT
VDD
R2 R1
1 2 3 4 5
10 F
6 7 8 9
0.1 F
10 F
10 11 12 13
Power-down
14 15
GSX NC AIN- NC SG NC VA NC AG NC VFRO NC NC DG PDN
ML7029
VD BCLK SYNC PCMSO PCMSI IS IR PCMRO PCMRI NC MCK DEN EXCK DIN DOUT
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCM I/F
ADPCM DATA
Master Clock
MCU I/F
19/29
FEDL7029-03
OKI Semiconductor
ML7029
APPLICATION INFORMATION
Burst Mode Clock This device can be operated by a burst mode clock (see below).
BCLK 1 2 3 4 5 6 7 8
SYNC 1/fsample s SYNC Signal Pulse Width : MIN. 1-bit clock : MAX. (Number of clocks in burst mode)-1
Figure 5 Example of Burst Mode Clock
Relationship between SYNC and BLCK
Transmit Side 1/fsample s SYNC BCLK 1 2 3 4 Ts PCMSI (1) A PCM Data Input 1s (Range of Data Slip Occurrence) 5 6 7 8
0.83/fsample s
Figure 6
Receive Side SYNC BCLK 1 Tr IR (2) 2 3 4 5 6 7 8 1/fsample s
ADPCM Data Input 1 s (Range of Data Slip Occurrence) 0.52/fsample s B
Figure 7
20/29
FEDL7029-03
OKI Semiconductor
ML7029
(1) PCMSI S/P Latch A SYNC Internal Clock Generation BCLK B ADPCM COD Latch P/S IS
(2) PCMRO P/S Latch ADPCM DEC Latch S/P IR
(1): PCM data serial to parallel conversion output (2): ADPCM data serial to parallel conversion output A: (1) Data internal latch timing B: (2) Data internal latch timing Figure 8
In this device, internal operating timing is generated according to the SYNC signal (see Figure 8). Therefore, a data slip may occur in the following timing when the PCM and ADPCM data is input. 1. When the PCM signal (PCMSI) is captured If TS: PCM signal output (1) after serial/parallel conversion and A: internal latch timing in Figure 6 overlap, a data slip occurs. 2. When the ADPCM signal (IR) is captured If Tr: ADPCM signal output (2) after serial/parallel conversion and B: internal latch timing in Figure 7 overlap, a data slip occurs. The data slip occurs at the timing of 1 and 2 above. Therefore, taking internal clock jitters and IC internal delay into consideration, the timing of SYNC and BCLK signals should not be set up in the range of about 1 s from the timing A and B.
21/29
FEDL7029-03
OKI Semiconductor
ML7029
REFERENCE DATA
Transmit Frequency Characteristics
Fs = 8 kHz Transmit BPF Characteristic 10 0 -10 -20 Gain (dB) -30 -40 -50 -60 -70 -80 100 1000 Frequency (Hz) 10000
Figure 9 Transmit Bandpass Filter Characteristic (Fs = 8 kHz, CR3-B1, B0 = (0, 0))
Fs = 8kHz Transmit LPF Characteristic 10 0 -10 -20 Gain (dB) -30 -40 -50 -60 -70 -80 100 1000 Frequency (Hz) 10000
Figure 10 Transmit Lowpass Filter Characteristic (Fs = 8 kHz, CR3-B1, B0 = (0, 1))
22/29
FEDL7029-03
OKI Semiconductor
ML7029
Fs = 11.025 kHz Transmit BPF Characteristic 10 0 -10 -20 Gain (dB) -30 -40 -50 -60 -70 -80 100 1000 Frequency (Hz) 10000
Figure 11 Transmit Bandpass Filter Characteristic (Fs = 11.025 kHz, CR3-B1, B0 = (1, 0))
Fs = 11.025 kHz Transmit LPF Characteristic 10 0 -10 -20 Gain (dB) -30 -40 -50 -60 -70 -80 100 1000 Frequency (Hz) 10000
Figure 12 Transmit Lowpass Filter Characteristic (Fs = 11.025 kHz, CR3-B1, B0 = (1, 1))
23/29
FEDL7029-03
OKI Semiconductor
ML7029
Receive Frequency Characteristics
Fs = 8 kHz Receive LPF Characteristic 10 0 -10 -20 Gain (dB) -30 -40 -50 -60 -70 -80 100 1000 Frequency (Hz) 10000
Figure 13 Receive Lowpass Filter Characteristic (Fs = 8 kHz, CR3-B1, B0 = (0, *))
Fs = 11.025 kHz Receive LPF Characteristic 10 0 -10 -20 Gain (dB) -30 -40 -50 -60 -70 -80 100 1000 Frequency (Hz) 10000
Figure 14 Receive Lowpass Filter Characteristic (Fs = 11.025 kHz, CR3-B1, B0 = (1, *))
24/29
FEDL7029-03
OKI Semiconductor
ML7029
APPENDIX
When the Sampling Frequency is 16 kHz or Higher: This device enables the operation at 16 kHz or higher sampling frequencies under conditions below. However, be aware that the AC characteristics are not guaranteed under these conditions.
Operating Conditions at Sampling Frequency = 19 kHz
Parameter Power Supply Voltage Operating Temperature Range Digital Input High Voltage Digital Input Low Voltage Master Clock Frequency Master Clock Frequency Accuracy Sampling Frequency Master Clock Duty Ratio Transmit S/N Ratio (at 3 dBm0 input) Transmit S/N Ratio (at -40 dBm0 input) Receive S/N Ratio (at 3 dBm0 input) Receive S/N Ratio (at -40 dBm0 input) Symbol VDD Ta VIH VIL fMCK1 fMCK2 fSYNC DMCK SD19T1 SD19T2 SD19R1 SD19R2 Condition Voltage must be fixed -- Digital input pin Digital input pin MCK MCK SYNC -- -- -- -- -- Min. 3.0 -25 0.95 x VDD 0 -- -0.01% -- 40 -- -- -- -- 24.624 SYNC x 1296 19 -- 46.2 24.8 45.4 38.0 Typ. -- -- -- Max. 3.6 +50 VDD 0.05 x VDD -- +0.01 -- 70 -- -- -- -- Unit V C V V MHz MHz kHz % dB dB dB dB
25/29
FEDL7029-03
OKI Semiconductor
ML7029
Operating Conditions at Sampling Frequency = 21 kHz
Parameter Power Supply Voltage Operating Temperature Range Digital Input High Voltage Digital Input Low Voltage Master Clock Frequency Master Clock Frequency Accuracy Sampling Frequency Master Clock Duty Ratio Transmit S/N Ratio (at 3 dBm0 input) Transmit S/N Ratio (at -40 dBm0 input) Receive S/N Ratio (at 3 dBm0 input) Receive S/N Ratio (at -40 dBm0 input) Symbol VDD Ta VIH VIL fMCK1 fMCK2 fSYNC DMCK SD19T1 SD19T2 SD19R1 SD19R2 Condition Voltage must be fixed -- Digital input pin Digital input pin MCK MCK SYNC -- -- -- -- -- Min. 3.3 -25 0.95 x VDD 0 -- -0.01% -- 40 -- -- -- -- 27.216 SYNC x 1296 21 -- 46.1 20.2 44.8 37.8 Typ. -- -- -- Max. 3.6 +50 VDD 0.05 x VDD -- +0.01 -- 70 -- -- -- -- Unit V C V V MHz MHz kHz % dB dB dB dB
26/29
FEDL7029-03
OKI Semiconductor
ML7029
PACKAGE DIMENSIONS
(Unit: mm)
SSOP30-P-56-0.65-K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.19 TYP. 5/Dec. 5, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
27/29
FEDL7029-03
OKI Semiconductor
ML7029
REVISION HISTORY
Document No.
FEDL7029-02
Date
Nov. 2001
Page Previous Current Edition Edition
- - - - 9 Final edition 2 Final edition 3
Description
FEDL7029-03
Feb.18, 2004 9
Changed "Symbol" of Setup Time and Hold Time for PCM/ ADPCM.
28/29
FEDL7029-03
OKI Semiconductor
ML7029
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2004 Oki Electric Industry Co., Ltd.
29/29

▲Up To Search▲

Price & Availability of ML7029

	To Download ML7029 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .